Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14210
-gerrit
commit 5ad0a02a16fe04f240db9eb3a6932eaca3a455c7 Author: Aaron Durbin adurbin@chromium.org Date: Thu Mar 31 11:38:13 2016 -0500
soc/intel/apollolake: use CAR code coherency for all CAR stages
The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image if flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases.
Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/bootblock/bootblock.c | 9 ------- src/soc/intel/apollolake/car.c | 33 ++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 41ac847..70ab515 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c +bootblock-y += car.c bootblock-y += gpio.c bootblock-y += mmap_boot.c bootblock-y += placeholders.c @@ -18,6 +19,7 @@ bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += placeholders.c +romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 4ea3f70..a9258e1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -12,7 +12,6 @@ #include <arch/cpu.h> #include <bootblock_common.h> #include <device/pci.h> -#include <program_loading.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/northbridge.h> @@ -36,14 +35,6 @@ void asmlinkage bootblock_c_entry(void) main(); }
-void platform_prog_run(struct prog *prog) -{ - /* Flush L1D cache to L2 */ - msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= (1 << 8); - wrmsr(MSR_POWER_MISC, msr); -} - void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c new file mode 100644 index 0000000..7646865 --- /dev/null +++ b/src/soc/intel/apollolake/car.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <program_loading.h> +#include <soc/cpu.h> + +/* + * This file supports the necessary hoops one needs to jump through since + * early FSP component and early stages are running from cache-as-ram. + */ + +static void flush_l1d_to_l2(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= (1 << 8); + wrmsr(MSR_POWER_MISC, msr); +} + +void platform_prog_run(struct prog *prog) +{ + /* Flush L1D cache to L2 */ + flush_l1d_to_l2(); +}