Attention is currently required from: Kangheui Won, Tim Wawrzynczak. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 )
Change subject: mb/google/nissa: Add devicetree ......................................................................
Patch Set 3: Code-Review+1
(5 comments)
Patchset:
PS3: LGTM but I don't have CR+2 yet.
File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61141/comment/f207be72_47a69c1b PS1, Line 4: register "pmc_gpe0_dw0" = "GPP_A" : register "pmc_gpe0_dw1" = "GPP_H" : register "pmc_gpe0_dw2" = "GPP_F"
These don't have to be sorted so bit of intention to minimize delta :)
Ack
https://review.coreboot.org/c/coreboot/+/61141/comment/97e583f9_a8a93e6b PS1, Line 24: USB2_C1
We'll need to handle it once we have fw_config.
Ack
https://review.coreboot.org/c/coreboot/+/61141/comment/274c1f5e_6e71934c PS1, Line 58: register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" : register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
To be honest I couldn't find any information about this, thus copied from brya & adlrvp_n.
That's probably reasonable for now. We can update later if needed.
https://review.coreboot.org/c/coreboot/+/61141/comment/e77e206c_2bef92bb PS1, Line 72: Sub-board
Thanks for catching it, updated comments.
Ack