[coreboot-gerrit] Change in coreboot[master]: sc7180: Remove QcLib specific changes from CB UART

[Julius Werner (Code Review)]

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42095 )

Change subject: sc7180: Remove QcLib specific changes from CB UART
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sc7180: Remove QcLib specific changes from CB UART

To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.

In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.

To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.

Signed-off-by: Roja Rani Yarubandi 
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/soc/qualcomm/sc7180/qupv3_config.c
M src/soc/qualcomm/sc7180/qupv3_uart.c
2 files changed, 3 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c
index b5adee2..3dbe3e6 100644
--- a/src/soc/qualcomm/sc7180/qupv3_config.c
+++ b/src/soc/qualcomm/sc7180/qupv3_config.c
@@ -54,10 +54,7 @@

/* HPG section 3.1.7.1 */
-	if (protocol == SE_PROTOCOL_UART) {
-		/* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */
-		clock_configure_qup(bus, QUPV3_UART_SRC_HZ);
-	} else {
+	if (protocol != SE_PROTOCOL_UART) {
    	setbits_le32(&regs->geni_dfs_if_cfg,
    			GENI_DFS_IF_CFG_DFS_IF_EN_BMSK);
    	/* configure clock dfsr */
diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c
index bf274c2..45d3d02 100644
--- a/src/soc/qualcomm/sc7180/qupv3_uart.c
+++ b/src/soc/qualcomm/sc7180/qupv3_uart.c
@@ -71,7 +71,7 @@
    /* sc7180 requires 16 clock pulses to sample 1 bit of data */
    uart_freq = baud_rate * 16;

-	div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq);
+	div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq);
    write32(&regs->geni_ser_m_clk_cfg, (div << 4) | 1);
    write32(&regs->geni_ser_s_clk_cfg, (div << 4) | 1);

@@ -147,7 +147,7 @@
    serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
    serial.baud = get_uart_baudrate();
    serial.regwidth = 4;
-	serial.input_hertz = QUPV3_UART_SRC_HZ;
+	serial.input_hertz = SRC_XO_HZ;

lb_add_serial(&serial, data);
 }