Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32334 ) Change subject: Documentation: Explain DDR3 read training ...................................................................... Patch Set 1: Code-Review+1 (12 comments) https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... File Documentation/getting_started/ram_initialization/ddr3_flyby.md: https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 6: is are https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 9: as on compared to the https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 9: did : terminat s/did terminate/terminated I think that the branches are also not good for high-speed signals, because of reflections and such. https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 12: The disadvantage of "fly-by" is the more complex memory training that needs to : be done to find the DATA lane skew. This is because the DDR2 tree results in all signals reaching the chips at the same time, whereas DDR3 fly-by means the signal reaches one chip after the other, hence the skew. https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 15: trailing space https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... File Documentation/getting_started/ram_initialization/readtraining.md: https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 7: MCH MCH is intel-specific, use "memory controller" instead. https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 13: MCH Same https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 27: usually usually? https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 98: trailing space https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 103: phase in From here onwards, lines are a bit too long https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 107: Samples Sample https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 105: The following algorithm is used: : : 1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern. : 2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low". : 3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern. : 4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge. : 5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge. : : Read training has now found the exact delay for each lane and stores the values for the next boot. This feature is known as *Fast Boot* or *MRC cache*. Sounds like Intel-specific. If you want to keep it like this, how about relating the usual names I've seen for rdtrain timings? I know of TAP and PI, with PI being the smallest one -- To view, visit https://review.coreboot.org/c/coreboot/+/32334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257 Gerrit-Change-Number: 32334 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis@fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Comment-Date: Fri, 30 Aug 2019 00:38:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment