Patch set 1:Code-Review +1
12 comments:
File Documentation/getting_started/ram_initialization/ddr3_flyby.md:
are
Patch Set #1, Line 9: as on
compared to the
did
terminat
s/did terminate/terminated
I think that the branches are also not good for high-speed signals, because of reflections and such.
The disadvantage of "fly-by" is the more complex memory training that needs to
be done to find the DATA lane skew.
This is because the DDR2 tree results in all signals reaching the chips at the same time, whereas DDR3 fly-by means the signal reaches one chip after the other, hence the skew.
trailing space
File Documentation/getting_started/ram_initialization/readtraining.md:
MCH is intel-specific, use "memory controller" instead.
Same
Patch Set #1, Line 27: usually
usually?
trailing space
Patch Set #1, Line 103: phase in
From here onwards, lines are a bit too long
Patch Set #1, Line 107: Samples
Sample
The following algorithm is used:
1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern.
2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low".
3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern.
4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge.
5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge.
Read training has now found the exact delay for each lane and stores the values for the next boot. This feature is known as *Fast Boot* or *MRC cache*.
Sounds like Intel-specific. If you want to keep it like this, how about relating the usual names I've seen for rdtrain timings? I know of TAP and PI, with PI being the smallest one
To view, visit change 32334. To unsubscribe, or for help writing mail filters, visit settings.