Attention is currently required from: Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email )
Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City ......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/intel/beechnutcity_crb/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/81322/comment/5c09b304_d9601d8e : PS12, Line 35: chip superio/common : device pnp 2e.0 on : chip superio/aspeed/ast2400 : register "use_espi" = "1" : device pnp 2e.2 on # SUART1 : io 0x60 = 0x3f8 # PNP_IDX_IO0 : irq 0x70 = 4 # PNP_IDX_IRQ0 : end : end : end : end : chip drivers/ipmi : device pnp ca2.0 on end # BMC KCS : register "wait_for_bmc" = "1" : register "bmc_boot_timeout" = "60" : end
Sorry, could you please specify?
The chip superio/common is not directly attached to the PCI domain but should be a child of a PCI device:
e.g. archercity has it below device 1f.0
device pci 1f.0 on # Intel device 1b81: PCH eSPI controller chip superio/common device pnp 2e.0 on chip superio/aspeed/ast2400 register "use_espi" = "1" device pnp 2e.2 on # SUART1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 on # SUART2 io 0x60 = 0x2f8 irq 0x70 = 3 end end end end chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end end