[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Paul Menzel, Tarun, Werner Zeh.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78079?usp=email )

Change subject: soc/intel: GMA v2 for ADL, MTL, TGL to reflect port/pipe defs
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78079/comment/317f911f_00c4fcd4 :
PS2, Line 18:
> I always wonder, why this can’t be detected at run-time by some PCI(?) (chipset) ID or so. Then no Kconfig option would be needed. Code size does not matter in this case, I think.

There is no such chipset ID to tell GMA v1 or v2 for say.

Also if you are interested to know what this Kconfig is guarding, then its register definition which is meant to be an uprev over the previous generation chipsets (starting with TGL)

https://review.coreboot.org/c/coreboot/+/78078/2/src/drivers/intel/gma/i915_...