[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00

[Ronak Kanabar (Code Review)]

Attention is currently required from: Bora Guvendik, V Sowmya, Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph.
Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Bernardo Perez Priego, Tim Wawrzynczak, Patrick Rudolph, V Sowmya, Tim Wawrzynczak, Meera Ravindranath, Srinidhi N Kaushik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/54083

to look at the new patch set (#4).

Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
......................................................................

vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00

The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.

BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.

Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: TBD
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/alderlake/meminit.c
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
3 files changed, 1,092 insertions(+), 1,090 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/54083/4