Patrick Rudolph (siro@das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10652
-gerrit
commit 923433711da066cc7dd7e50ce065bf6cb065e74f Author: Patrick Rudolph siro@das-labor.org Date: Wed Jun 24 19:14:53 2015 +0200
raminit native: properly handle DDR3 DIMMs with address mirroring
Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty.
Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM)
Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot.
Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph siro@das-labor.org --- src/northbridge/intel/sandybridge/raminit_native.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a569411..0fda94d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -832,11 +832,6 @@ static void dram_dimm_mapping(dimm_info * info, ramctr_timing * ctrl) dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; reg |= (1 << 16); - // swap dimm info - t = ctrl->rank_mirror[channel][1]; - ctrl->rank_mirror[channel][1] = - ctrl->rank_mirror[channel][3]; - ctrl->rank_mirror[channel][3] = t; } // dimmA if (dimmA && (dimmA->ranks > 0)) { @@ -1231,6 +1226,9 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, printram("MRd: %x <= %x\n", reg, val);
if (ctrl->rank_mirror[channel][slotrank]) { + /* DDR3 Rank1 Address mirror + * swap the following pins: + * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1);