Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28766
Change subject: amd/stoneyridge: Add USB settings to gnvs ......................................................................
amd/stoneyridge: Add USB settings to gnvs
A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure.
The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build.
The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear.
BUG=b:77602074
Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 2 files changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28766/1
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index f77d108..6d38d6b 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -65,6 +65,11 @@ , 2, ESPI, 1, // ESPI, 27 , 4, + FW00, 16, // 0x35 - xHCI FW ROM addr, boot RAM + FW01, 32, // 0x37 - xHCI FW RAM addr, boot RAM + FW02, 16, // 0x3B - xHCI FW ROM addr, Instruction RAM + FW03, 32, // 0x3D - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x41 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 667f6ef..8fa3236 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -52,7 +52,12 @@ uint8_t tpsv; /* 0x2F - Passive Threshold */ uint8_t tmax; /* 0x30 - CPU Tj_max */ aoac_devs_t aoac; /* 0x31 - AOAC device enables */ - uint8_t unused[203]; + uint16_t fw00; /* 0x35 - XhciFwRomAddr_Rom, Boot RAM */ + uint32_t fw01; /* 0x37 - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint16_t fw02; /* 0x3B - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw03; /* 0x3D - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x41 - EHCI BAR */ + uint8_t unused[187];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;