Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39232 )
Change subject: soc/intel/tigerlake: Enable Hybride storage mode ......................................................................
soc/intel/tigerlake: Enable Hybride storage mode
Enable Hybrid storage auto detection
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check Pcie lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 02855b1..5cd3798 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -262,6 +262,9 @@ uint8_t DdiPort2Ddc; uint8_t DdiPort3Ddc; uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable(1)/disable(0) */ + uint8_t HybridStorageMode; };
typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde0..edf07c9 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,9 @@ sizeof(params->SataPortsDevSlp)); }
+ /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;