[coreboot-gerrit] Change in coreboot[master]: [HACK,NOTFORMERGE]: Don't include some code...

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36435 )

Change subject: [HACK,NOTFORMERGE]: Don't include some code...
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[HACK,NOTFORMERGE]: Don't include some code...

Used to make use of SOUTHBRIDGE_INTEL_COMMON in soc/intel.

Change-Id: Ib719fb6524fff70be3730dc1786ae778f2750c43
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/Makefile.inc
1 file changed, 15 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/36435/1

diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index deab85f..6bebd3c 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -16,11 +16,11 @@
 # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
 subdirs-y += firmware

-verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
-bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
-romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
-ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
-postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+# verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+# bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+# romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+# ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+# postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c

romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
 ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
@@ -31,11 +31,11 @@

ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)

-verstage-y += pmbase.c
-romstage-y += pmbase.c
-ramstage-y += pmbase.c
-postcar-y += pmbase.c
-smm-y += pmbase.c
+# verstage-y += pmbase.c
+# romstage-y += pmbase.c
+# ramstage-y += pmbase.c
+# postcar-y += pmbase.c
+# smm-y += pmbase.c

bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c
@@ -63,10 +63,10 @@

smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c

-verstage-y += rtc.c
-romstage-y += rtc.c
-ramstage-y += rtc.c
-postcar-y += rtc.c
-smm-y += rtc.c
+# verstage-y += rtc.c
+# romstage-y += rtc.c
+# ramstage-y += rtc.c
+# postcar-y += rtc.c
+# smm-y += rtc.c

endif