Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43928 )
Change subject: mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` lines ......................................................................
mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` lines
They default to zero already, so we might as well drop them.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I3c04240b270f51d584f879e1344301679f133fdb Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43928 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb 1 file changed, 0 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 50767bb..7996791 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,19 +14,15 @@ # PCIe configuration # Enable JPCIE1 register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "0"
# Enable ASpeed PCI bridge register "PcieRpEnable[2]" = "1" - register "PcieRpClkReqSupport[2]" = "0"
# Enable X550T (10GbE) register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0"
# Enable M.2 register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "0"
# FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1"