Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6381
-gerrit
commit 9822b0c22448c08d29b6a3b980ce1901471132af Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Jul 28 00:21:44 2014 +1000
mainboard/jetway/nf86-t56n-lf: acpi/cpu.asl TZ throttle
The intent here is to implement CPU clock throttling for this f14 board as to be used in the thermal zone for the passive cooling profile.
This still needs some work, RFC at this stage.
Change-Id: I0b77d1fbf7459c62f4ea694e002e10fd3b1879ce Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/jetway/nf81-t56n-lf/acpi/cpu.asl | 70 ++++++++++++++++++++++++++ 1 file changed, 70 insertions(+)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/cpu.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/cpu.asl new file mode 100644 index 0000000..a964c0d --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/cpu.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(CPU0) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + + // Processor Throttle Control object + Name(_PTC, ResourceTemplate() { + Register(SystemIO, 32, 0, 0x120) // Processor Control + Register(SystemIO, 32, 0, 0x120) // Processor Status + }) + + // Throttling Supported States + // The values shown are for exemplary purposes only + Name(_TSS, Package() { + // Read: freq percentage, power, latency, control, status + Package() {0x64, 1000, 0x0, 0x7, 0x0}, // Throttle off (100%) + Package() {0x58, 800, 0x0, 0xF, 0x0}, // 87.5 % + Package() {0x4B, 600, 0x0, 0xE, 0x0}, // 75% + Package() {0x3F, 400, 0x0, 0xD, 0x0} // 62.5% + }) + + // Throttling Present Capabilities + Method(_TPC) { + Return (0) // All throttle states available + } +} + +Device(CPU1) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + + // Processor Throttle Control object + Name(_PTC, ResourceTemplate() { + Register(SystemIO, 32, 0, 0x120) // Processor Control + Register(SystemIO, 32, 0, 0x120) // Processor Status + }) + + // Throttling Supported States + // The values shown are for exemplary purposes only + Name(_TSS, Package() { + // Read: freq percentage, power, latency, control, status + Package() {0x64, 1000, 0x0, 0x7, 0x0}, // Throttle off (100%) + Package() {0x58, 800, 0x0, 0xF, 0x0}, // 87.5 % + Package() {0x4B, 600, 0x0, 0xE, 0x0}, // 75% + Package() {0x3F, 400, 0x0, 0xD, 0x0} // 62.5% + }) + + // Throttling Present Capabilities + Method(_TPC) { + Return (0) // All throttle states available + } +}