Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found official documentation for the DXIO lane mapping on Pollock, so I haven't added a table for that yet.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/44063/1
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 2faa0ab..b99980f 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -113,6 +113,28 @@ * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure * bifurcation and other settings. Beware that the lane numbers in here are the logical and not * the physical lane numbers! + * + * Picasso DXIO lane mapping: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[7:0] | [15:8] | PCIe + * GPP[3:0] | [7:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | PCIe, SATA + * + * Dali has less DXIO connectivity than Picasso: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[3:0] | [11:8] | PCIe + * GPP[1:0] | [5:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | SATA + * + * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane + * numbers differs to Picasso/Dali. Only logical lanes [1:0] and [5:4] are present and they + * only support PCIe. */ typedef struct __packed { uint8_t engine_type;