Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3518
-gerrit
commit 050fd145ff63458ac02c985a7a852015730aec8b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Jun 22 21:27:20 2013 +0300
CBMEM: high_table globals cleanup [NOTFORMERGE]
Squashed for abuild only.
Change-Id: I910842f51ead98af7a85c20c90dd230e6a6458ed Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/armv7/boot/tables.c | 13 +-- src/arch/x86/boot/Makefile.inc | 3 + src/arch/x86/boot/ramtop.c | 60 ++++++++++++ src/arch/x86/boot/tables.c | 12 +-- src/arch/x86/include/arch/io.h | 14 +++ src/cpu/amd/agesa/s3_resume.c | 11 +-- src/cpu/amd/car/post_cache_as_ram.c | 9 +- src/include/cbmem.h | 18 ++-- src/lib/cbmem.c | 109 ++++++++++++++------- src/lib/coreboot_table.c | 5 - src/mainboard/emulation/qemu-i440fx/memory.c | 8 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 +- src/mainboard/getac/p470/romstage.c | 5 +- src/mainboard/google/snow/ramstage.c | 13 ++- src/mainboard/google/stout/romstage.c | 3 +- src/mainboard/ibase/mb899/romstage.c | 5 +- src/mainboard/intel/d945gclf/romstage.c | 5 +- src/mainboard/kontron/986lcd-m/romstage.c | 5 +- src/mainboard/roda/rk886ex/romstage.c | 5 +- src/mainboard/roda/rk9/romstage.c | 5 +- src/northbridge/amd/agesa/family10/northbridge.c | 18 +--- src/northbridge/amd/agesa/family12/northbridge.c | 23 +---- src/northbridge/amd/agesa/family14/northbridge.c | 22 +---- src/northbridge/amd/agesa/family15/northbridge.c | 18 +--- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +--- src/northbridge/amd/amdfam10/northbridge.c | 18 +--- src/northbridge/amd/amdk8/northbridge.c | 18 +--- src/northbridge/amd/gx1/northbridge.c | 4 +- src/northbridge/amd/gx2/northbridge.c | 4 +- src/northbridge/amd/lx/northbridge.c | 4 +- src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/amd/lx/northbridgeinit.c | 2 +- src/northbridge/intel/e7501/northbridge.c | 4 +- src/northbridge/intel/e7505/northbridge.c | 4 +- src/northbridge/intel/e7505/raminit.h | 1 - src/northbridge/intel/e7520/northbridge.c | 4 +- src/northbridge/intel/e7525/northbridge.c | 4 +- src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/gm45/northbridge.c | 4 +- src/northbridge/intel/gm45/ram_calc.c | 2 +- src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/i3100/northbridge.c | 4 +- src/northbridge/intel/i440bx/northbridge.c | 4 +- src/northbridge/intel/i440lx/northbridge.c | 4 +- src/northbridge/intel/i5000/northbridge.c | 5 +- src/northbridge/intel/i82810/northbridge.c | 4 +- src/northbridge/intel/i82830/northbridge.c | 4 +- src/northbridge/intel/i855/northbridge.c | 4 +- src/northbridge/intel/i945/northbridge.c | 4 +- src/northbridge/intel/i945/raminit.c | 5 - src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 19 +--- src/northbridge/intel/sandybridge/raminit.c | 5 - src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/intel/sch/northbridge.c | 6 +- src/northbridge/rdc/r8610/northbridge.c | 4 +- src/northbridge/via/cn400/northbridge.c | 5 +- src/northbridge/via/cn700/northbridge.c | 5 +- src/northbridge/via/cx700/northbridge.c | 5 +- src/northbridge/via/vt8601/northbridge.c | 5 +- src/northbridge/via/vt8623/northbridge.c | 5 +- src/northbridge/via/vx900/early_vx900.c | 5 - src/northbridge/via/vx900/early_vx900.h | 1 - src/northbridge/via/vx900/northbridge.c | 6 +- src/southbridge/amd/agesa/hudson/early_setup.c | 5 +- src/southbridge/amd/agesa/hudson/hudson.c | 9 +- src/southbridge/amd/cimx/sb700/lpc.c | 5 +- src/southbridge/amd/cimx/sb800/cfg.c | 9 +- src/southbridge/amd/cimx/sb800/early.c | 1 - src/southbridge/amd/cimx/sb800/lpc.c | 1 - src/southbridge/amd/sb700/early_setup.c | 5 +- src/southbridge/amd/sb700/lpc.c | 5 +- src/southbridge/amd/sb800/early_setup.c | 5 +- src/southbridge/via/k8t890/early_car.c | 5 +- src/southbridge/via/k8t890/host_ctrl.c | 9 +- 75 files changed, 261 insertions(+), 396 deletions(-)
diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index 0fc7399..de6b6fa 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -29,13 +29,6 @@
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
-/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - void cbmem_arch_init(void) { } @@ -44,11 +37,7 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer;
- if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + cbmem_base_check();
post_code(0x9d);
diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 7b67e49..89faabe 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,7 +1,10 @@ +romstage-y += ramtop.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c ramstage-y += tables.c +ramstage-y += ramtop.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c new file mode 100644 index 0000000..c218869 --- /dev/null +++ b/src/arch/x86/boot/ramtop.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <cbmem.h> + +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* do nothing, this should be called by chipset to save TOC in NVRAM */ +} + +#if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void set_top_of_ram(uint64_t ramtop) +{ + backup_top_of_ram(ramtop); + set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE, 1); +} + +void set_top_of_ram_once(uint64_t ramtop) +{ + backup_top_of_ram(ramtop); + set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE, 0); +} +#endif diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 6355a1b..74ac76f 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -32,8 +32,6 @@ #include <lib.h> #include <smbios.h>
-uint64_t high_tables_base = 0; -uint64_t high_tables_size;
void cbmem_arch_init(void) { @@ -45,6 +43,7 @@ struct lb_memory *write_tables(void) { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; + u64 high_tables_base = 0;
/* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -53,13 +52,8 @@ struct lb_memory *write_tables(void) unsigned long high_table_pointer;
#if !CONFIG_DYNAMIC_CBMEM - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); + cbmem_base_check(); + high_tables_base = (u32)get_cbmem_toc(); #endif
rom_table_start = 0xf0000; diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..c5425bf 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -506,5 +506,19 @@ static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsi
#endif /* __PRE_RAM__ */
+/* x86 CBMEM helpers */ + +#ifndef __ROMCC__ +/* ROMCC has no uint64_t. */ +unsigned long get_top_of_ram(void); +void backup_top_of_ram(uint64_t ramtop); +uint64_t restore_top_of_ram(void); + +#ifndef __PRE_RAM__ +void set_top_of_ram(uint64_t ramtop); +void set_top_of_ram_once(uint64_t ramtop); +#endif +#endif + #endif
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 8a9ffee..9b60815 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -109,18 +109,9 @@ void restore_mtrr(void)
inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory;
- /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - /* - * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); - * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - */ - - cbmem_reinit((u64) high_ram_base); + cbmem_reinit();
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (((u32) resume_backup_memory == 0) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 68e7c09..a530c93 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -32,20 +32,13 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi #if CONFIG_HAVE_ACPI_RESUME
static inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory; int suspend = acpi_is_wakeup_early();
if (!suspend) return NULL;
- /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); - print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - - cbmem_reinit((u64)high_ram_base); + cbmem_reinit();
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efb0f90..92f61ce 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -125,23 +125,18 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry);
-#ifndef __PRE_RAM__ -/* Add the cbmem memory used to the memory tables. */ -struct lb_memory; -void cbmem_add_lb_mem(struct lb_memory *mem); -#endif /* __PRE_RAM__ */
#else /* !CONFIG_DYNAMIC_CBMEM */
#ifndef __PRE_RAM__ -extern uint64_t high_tables_base, high_tables_size; -void set_cbmem_toc(struct cbmem_entry *); +int cbmem_base_check(void); #endif
-void cbmem_init(u64 baseaddr, u64 size); -int cbmem_reinit(u64 baseaddr); +int cbmem_reinit(void);
-extern struct cbmem_entry *get_cbmem_toc(void); +struct cbmem_entry *get_cbmem_toc(void); +void get_cbmem_table(uint64_t *base, uint64_t *size); +void set_cbmem_table(uint64_t base, uint64_t size, int force);
#endif /* CONFIG_DYNAMIC_CBMEM */
@@ -159,6 +154,9 @@ void *cbmem_find(u32 id);
#ifndef __PRE_RAM__ /* Ramstage only functions. */ +/* Add the cbmem memory used to the memory tables. */ +struct lb_memory; +void cbmem_add_lb_mem(struct lb_memory *mem); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 3702da1..7730464 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,7 @@ #include <string.h> #include <bootstate.h> #include <cbmem.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -42,27 +43,59 @@ struct cbmem_entry { } __attribute__((packed));
#ifndef __PRE_RAM__ -static struct cbmem_entry *bss_cbmem_toc; +static uint64_t bss_cbmem_base = 0; +static uint64_t bss_cbmem_size = 0; +#endif
-struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +static unsigned long cbmem_base(void) { - return bss_cbmem_toc; +#ifdef __PRE_RAM__ + u64 base, size; + get_cbmem_table(&base, &size); + return (unsigned long)base; +#else + if (!(bss_cbmem_base && bss_cbmem_size)) + get_cbmem_table(&bss_cbmem_base, &bss_cbmem_size); + return (unsigned long)bss_cbmem_base; +#endif }
-void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +static unsigned long cbmem_size(void) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} +#ifdef __PRE_RAM__ + u64 base, size; + get_cbmem_table(&base, &size); + return (unsigned long)size; #else + if (!(bss_cbmem_base && bss_cbmem_size)) + get_cbmem_table(&bss_cbmem_base, &bss_cbmem_size); + return (unsigned long)bss_cbmem_size; +#endif +} +#endif
-struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void set_cbmem_table(uint64_t base, uint64_t size, int force) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; -} + if (base == bss_cbmem_base && size == bss_cbmem_size) + return;
+ if (!force && bss_cbmem_base) { + printk(BIOS_ERR, "CBMEM region %llx-%llx (not moved)\n", base, base+size-1); + } else { + printk(BIOS_DEBUG, "CBMEM region %llx-%llx\n", base, base+size-1); + bss_cbmem_base = base; + bss_cbmem_size = size; + } +} #endif
+struct cbmem_entry *get_cbmem_toc(void) +{ + return (struct cbmem_entry *)cbmem_base(); +} + /** * cbmem is a simple mechanism to do some kind of book keeping of the coreboot * high tables memory. This is a small amount of memory which is "stolen" from @@ -73,14 +106,12 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) * - suspend/resume backup memory */
-void cbmem_init(u64 baseaddr, u64 size) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +static void cbmem_init(void) { + unsigned long long baseaddr = cbmem_base(); + unsigned long long size = cbmem_size(); struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif
printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -90,10 +121,7 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; }
- /* we don't need to call this in romstage, usefull only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif + cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; memset(cbmem_toc, 0, CBMEM_TOC_RESERVED);
cbmem_toc[0] = (struct cbmem_entry) { @@ -103,18 +131,16 @@ void cbmem_init(u64 baseaddr, u64 size) .size = size - CBMEM_TOC_RESERVED }; } +#endif
-int cbmem_reinit(u64 baseaddr) +int cbmem_reinit(void) { + unsigned long baseaddr = (unsigned long) get_cbmem_toc(); struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; + cbmem_toc = (struct cbmem_entry *)baseaddr;
printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", - (unsigned long)baseaddr); - -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif + baseaddr);
return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -210,20 +236,14 @@ int cbmem_initialize(void) { int rv = 0;
-#ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif - /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit()) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(); rv = 1; } #ifndef __PRE_RAM__ @@ -250,6 +270,25 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), };
+int cbmem_base_check(void) +{ + u64 base = cbmem_base(); + if (!base) { + printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); + // Are there any boards without? + // Stepan thinks we should die() here! + } + printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", base); + return !!base; +} + +void cbmem_add_lb_mem(struct lb_memory *mem) +{ + u64 base = cbmem_base(); + u64 size = cbmem_size(); + lb_add_memory_range(mem, LB_MEM_TABLE, base, size); +} + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d25b59d..0c16c42 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -539,12 +539,7 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end - rom_table_start);
-#if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); -#else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); -#endif /* CONFIG_DYNAMIC_CBMEM */
/* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..027deb9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,18 +40,12 @@ static unsigned long qemu_get_memory_size(void) return tomk; }
-unsigned long get_top_of_ram(void); unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; }
-#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 3e45d9a..0afcaed 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -54,9 +54,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) ram_resource(dev, idx++, 4 * 1024 * 1024, high);
#if !CONFIG_DYNAMIC_CBMEM - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); #endif
/* Reserve space for the IOAPIC. This should be in the Southbridge, diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90d38eb..f4e43e5 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -358,13 +358,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 72f830d..ac44d1d 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -76,6 +76,13 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) framebuffer->reserved_mask_size = 0; }
+void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + *base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + *size = CONFIG_COREBOOT_TABLES_SIZE; +}
void hardwaremain(void); void main(void) @@ -83,11 +90,7 @@ void main(void) /* FIXME this should be moved elsewhere. We don't want ramstage.c */
/* set up coreboot tables */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + cbmem_initialize();
/* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 14820dd..83be94e 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -313,8 +313,7 @@ void main(unsigned long bist) #if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); #else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); + cbmem_was_initted = cbmem_reinit(); #endif
#if CONFIG_HAVE_ACPI_RESUME diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 79eaa0b..b059a57 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -312,13 +312,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a37f605..248aa3b 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -270,13 +270,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 03b24d8..324f442 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -411,13 +411,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ab200d2..cb141f9 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -347,13 +347,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 56eea84..075790d 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -184,13 +184,10 @@ void main(unsigned long bist) init_iommu();
#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit((u64)high_ram_base)) { + if (s3resume && cbmem_reinit() { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 4589f6d..325d2c1 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } }
#if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 621246f..4c230f1 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), - high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size);
#if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e7de273..fbf8e44 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4 * 1024 * 1024) { @@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size);
#if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6134830..7e33046 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } }
#if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f91f690..2e1ff2e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } }
#if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 2228fb5..be77f8b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; sizek -= pre_sizek;
- if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } }
#if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5c1d97a..505d94d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } }
#if CONFIG_GFXUMA diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index d670a19..3db3974 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -108,9 +108,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024);
/* Report the memory regions */ idx = 10; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 038d757..27de1a4 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -290,9 +290,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); }
assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index bde72a7..4df6879 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -389,9 +389,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); }
assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index fd62184..25075bd 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -28,7 +28,6 @@ int sizeram(void);
/* northbridgeinit.c */ void northbridge_init_early(void); -uint32_t get_top_of_ram(void);
/* pll_reset.c */ unsigned int GeodeLinkSpeed(void); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 3768777..ba9db2b 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -713,7 +713,7 @@ static void setup_lx_cache(void) wbinvd(); }
-uint32_t get_top_of_ram(void) +unsigned long get_top_of_ram(void) { struct gliutable *gl = 0; uint32_t systop; diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index d30c9df..0dc7b0b 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -84,9 +84,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6ee371f..4b24b79 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -85,9 +85,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f9ba796..8eb4990 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void);
-unsigned long get_top_of_ram(void);
/* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 96fcc35..8b74cec 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -102,9 +102,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 83757bd..402dbda 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -101,9 +101,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 2dffcad..227baef 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -422,7 +422,6 @@ void gm45_late_init(stepping_t);
u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); -u32 get_top_of_ram(void);
void init_iommu(void); #endif diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 3a4439c..d55a03a 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -166,9 +166,7 @@ static void mch_domain_read_resources(device_t dev) pcie_config_size >> 10, IORESOURCE_RESERVE); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk << 10); }
static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 9e54c10..8c4357f 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -83,7 +83,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } }
-u32 get_top_of_ram(void) +unsigned long get_top_of_ram(void) { const device_t dev = PCI_DEV(0, 0, 0);
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 46be570..706c286 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -23,7 +23,6 @@ #include "pei_data.h"
void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index bcaded6..b3349ed 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -126,9 +126,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); }
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 2ab62a9..c1aec92 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,9 +67,7 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index fe5f09e..b41a975 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -93,9 +93,7 @@ static void i440lx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 113dc56..3e186fa 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -111,10 +111,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = tolm - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); + set_top_of_ram(tolm); }
static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 1d6b66d..3fb3e11 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -121,9 +121,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, tomk - 768); uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024);
assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 881551c..73c28dd 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -90,9 +90,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); }
static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 75837a1..4c1cd93 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -105,9 +105,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..fc84647 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -170,9 +170,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); }
/* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h>
-struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..9eb4193 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,7 +69,6 @@ struct sys_info {
void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us);
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index d8e2e9d..4097b6c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,21 +51,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; }
-static unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); - return (unsigned long) tom; -} - -struct cbmem_entry *get_cbmem_toc(void) -{ - static struct cbmem_entry *toc = NULL; - if (!toc) - toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); - return toc; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA @@ -274,9 +259,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); }
/* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 78eedb8..e1fb7f4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); }
-struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 23bdbd9..2e9b1f3 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,7 +30,6 @@ struct sys_info { } __attribute__ ((packed));
void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_sandybridge_errata(void);
#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 06d34d8..7cf1db3 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -182,11 +182,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
- /* Leave some space for ACPI, PIRQ and MP tables. */ - high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; - high_tables_base -= uma_memory_size; - high_tables_base -= tseg_memory_base; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024 - uma_memory_size - tseg_memory_base); }
/* diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index e97f10a..2c830ec 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -64,9 +64,7 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024);
assign_resources(dev->link_list); } diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 0108170..e78d836 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -204,10 +204,7 @@ static void cn400_domain_set_resources(device_t dev) }
/* Locate the High Tables at the Top of Low Memory below the Video RAM */ - high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024);
/* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 73bf676..c5305d8 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -134,10 +134,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; }
- high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
/* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index f28a0ed..0d57772 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -68,10 +68,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory }
- high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024);
/* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 45a0ac5..aa775f7 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -84,10 +84,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; }
- high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024);
/* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index f93a886..dd0271a 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -143,10 +143,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; }
- high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024);
/* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); }
-struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. * diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index dcb24b5..46e3023 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -61,7 +61,6 @@ #define RAMINIT_USE_HW_RXCR_CALIB 0 #define RAMINIT_USE_HW_MRS_SEQ 0
-unsigned long get_top_of_ram(void);
void enable_smbus(void); void dump_spd_data(spd_raw_data spd); diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index c3c3920..35e2261 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -266,11 +266,7 @@ static void vx900_set_resources(device_t dev) u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);
- /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + set_top_of_ram(tolmk << 10);
print_debug("======================================================\n"); assign_resources(dev->link_list); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..408f56e 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <reset.h> #include <arch/cpu.h> -#include <cbmem.h> #include "hudson.h"
void hudson_lpc_port80(void) @@ -95,7 +94,7 @@ int acpi_is_wakeup_early(void) } #endif
-struct cbmem_entry *get_cbmem_toc(void) +uint64_t restore_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +104,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (uint64_t) xdata; }
#endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..7546dae 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -26,7 +26,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cbmem.h> #include "hudson.h" #include "smbus.h"
@@ -40,9 +39,9 @@ int acpi_get_sleep_type(void) } #endif
-void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,7 +131,7 @@ void hudson_enable(device_t dev) } }
-struct cbmem_entry *get_cbmem_toc(void) +uint64_t restore_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -142,7 +141,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (uint64_t) xdata; }
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..0b317ff 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -22,14 +22,13 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <console/console.h> /* printk */ -#include <cbmem.h>
#define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5
-void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..8538e1d 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -21,7 +21,6 @@ #include "SBPLATFORM.h" #include "cfg.h" #include "OEM.h" -#include <cbmem.h>
#include <arch/io.h> #include <arch/acpi.h> @@ -37,9 +36,9 @@ int acpi_get_sleep_type(void) #endif
#ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,7 +50,7 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif
-struct cbmem_entry *get_cbmem_toc(void) +uint64_t restore_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; @@ -61,7 +60,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (uint64_t) xdata; }
/** diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 83087f5..8b4c961 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -24,7 +24,6 @@ #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ -#include "cbmem.h"
#if CONFIG_RAMINIT_SYSINFO /** diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a1e0dc9..70b9a91 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -23,7 +23,6 @@ #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> -#include <cbmem.h>
void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..4604bc6 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -28,7 +28,6 @@
#include <reset.h> #include <arch/cpu.h> -#include <cbmem.h> #include "sb700.h" #include "smbus.h"
@@ -731,7 +730,7 @@ int acpi_is_wakeup_early(void) } #endif
-struct cbmem_entry *get_cbmem_toc(void) +uint64_t restore_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -741,7 +740,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (uint64_t) xdata; }
#endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..7712cc0 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -27,7 +27,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <cbmem.h> #include "sb700.h"
static void lpc_init(device_t dev) @@ -84,9 +83,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); }
-void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..3410b1b 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -22,7 +22,6 @@
#include <reset.h> #include <arch/cpu.h> -#include <cbmem.h> #include "sb800.h" #include "smbus.c"
@@ -675,7 +674,7 @@ static int acpi_is_wakeup_early(void) } #endif
-struct cbmem_entry *get_cbmem_toc(void) +uint64_t restore_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -685,7 +684,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (uint64_t) xdata; }
#endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..2a9f5ec 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -24,7 +24,6 @@ */
#include <stdlib.h> -#include <cbmem.h> #include <arch/io.h> #include "k8x8xx.h"
@@ -183,6 +182,6 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; }
-struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +uint64_t restore_top_of_ram(void) { + return (uint64_t) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); } diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..3452195 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include <cbmem.h> #include <arch/io.h> #include "k8x8xx.h"
@@ -114,12 +113,12 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) {
} #if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +uint64_t restore_top_of_ram(void) { + return (uint64_t) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); } #endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); }
static struct pci_operations lops_pci = {