Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30436
Change subject: mb/google/hatch: Enable CNVi Wifi and Bluetooth for hatch ......................................................................
mb/google/hatch: Enable CNVi Wifi and Bluetooth for hatch
This patch incorporates following changes to enable CNVi bluetooth and Wifi. 1. Enable CNVi PCI device 14.3 2. Enable USB port 5 for Bluetooth 3. Enable PCI clock source 3 4. Configure GPIO pads for CNVi, BT and WLAN.
BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics
Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30436/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 731ebba..ee73f9e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,6 +44,10 @@ register "InternalGfx" = "1" register "SkipExtGfxScan" = "1"
+ # USB PORT 5 for BT and WLAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + + register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -53,6 +57,10 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 off end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/generic @@ -64,7 +72,7 @@ end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.3 on end # I2C #3 device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 9f7512c..b4aedab 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -63,6 +63,33 @@ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* MODEM_CLKREQ */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* CNV_BT_I2S_SCLK */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF2), + /* UART_WWANRX_WLANTX_COEX2 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* UART_WWANTX_WLANRX_COEX1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + /* CNV_RGI_DT_R */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + /* CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + /* GPIO_WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), + /* PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI(GPP_C1, NONE, PLTRST), + /* PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + };
const struct pad_config *__weak variant_gpio_table(size_t *num)