Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81033?usp=email )
Change subject: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/81033/comment/300b2d55_1a5171a9 : PS1, Line 197: /*Add virtual GPIOs for CPU PCIe RP*/
nit: […]
I just copied this GPIO group from https://review.coreboot.org/c/coreboot/+/57875. I was able to get a hint from this comment, how about keep it?
https://review.coreboot.org/c/coreboot/+/81033/comment/4d46a478_dbb4865a : PS1, Line 198: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
btw, wondering what was the value before and after your gpio programming. […]
I just copied it from https://review.coreboot.org/c/coreboot/+/57875. NVME couldn't work properly without this CL, so the chipset default config should not be native function. I couldn't find the reference for vGPIOs, can you look at the bug - b:200886824? (Can I get access for this bug as well?)