Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Anjaneya "Reddy" Chagam, Damien Zammit, Lee Leahy, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Tim Chu, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63595 )
Change subject: arch/x86/postcar_loader.c: Provide a NOOP weak postcar_fill_frame ......................................................................
arch/x86/postcar_loader.c: Provide a NOOP weak postcar_fill_frame
Most implementations do nothing so it makes sense to have a weakly linked function doing just that.
Change-Id: Ifd28905c03e31700b4a5f0e58779eaca6784c1ad Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar_loader.c M src/drivers/intel/fsp1_1/car.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/xeon_sp/memmap.c 16 files changed, 6 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63595/1
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index d637d19..2ce7d53 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -35,7 +35,7 @@ * fill_postcar_frame() is called after raminit completes and right before * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() * to tag memory ranges as cacheable to speed up execution of postcar and - * early ramstage. + * early ramstage. There is a weak implementation doing nothing. */ void fill_postcar_frame(struct postcar_frame *pcf);
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 0545210..577ef8b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -94,6 +94,11 @@
static void run_postcar_phase(struct postcar_frame *pcf);
+/* Only implement this if a platform needs to override common MTRR setup */ +__weak void fill_postcar_frame(struct postcar_frame *pcf) +{ +} + /* prepare_and_run_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void prepare_and_run_postcar(void) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 65cf3d4..ed51d0c 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -10,10 +10,6 @@ #include <fsp/car.h> #include <fsp/util.h>
-void fill_postcar_frame(struct postcar_frame *pcf) -{ -} - /* This is the romstage entry called from cpu/intel/car/romstage.c */ void mainboard_romstage_entry(void) { diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 2e98cf0..73cd6ad5 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -115,7 +115,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 84fe86f..09b0810 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -66,7 +66,3 @@
*size -= *start; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 321421c..e8d6891 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -50,7 +50,3 @@ } return (void *)tom; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 556b9a7..79e2004 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -80,7 +80,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index de34a38..c2989ab 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -32,7 +32,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index fa1c873..dcd25f4 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -84,7 +84,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 0df49ed..2ff9b57 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -64,7 +64,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index f942c09..d3d809f 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -82,7 +82,3 @@ *start = northbridge_get_tseg_base(); *size = northbridge_get_tseg_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index f78d2f0..ddf5aff 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -123,10 +123,6 @@ prepare_and_run_postcar(); }
-void fill_postcar_frame(struct postcar_frame *pcf) -{ -} - void SetMemParams(AMD_POST_PARAMS *PostParams) { const struct soc_amd_stoneyridge_config *cfg; diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 5987e0b..096e264 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -26,7 +26,3 @@ *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f0d7b76..7b9cd1a 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -44,7 +44,3 @@ *start = tseg; *size = bgsm - tseg; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index c417ee1..2acbb51 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -38,7 +38,3 @@ *start = smm_region_start(); *size = smm_region_size(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ -} diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 2586e7e..2a56d98 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -27,10 +27,6 @@ *size = tseg_limit - tseg_base; }
-void fill_postcar_frame(struct postcar_frame *pcf) -{ -} - #if !defined(__SIMPLE_DEVICE__) union dpr_register txt_get_chipset_dpr(void) {