Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36286 )
Change subject: soc/mediatek/mt8183: Pass MR values as function arguments ......................................................................
Patch Set 3:
(1 comment)
please enable the DRAM calibration log and capture the partition bootup log to check whether MR setting result same as original code.
https://review.coreboot.org/c/coreboot/+/36286/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/36286/2/src/soc/mediatek/mt8183/dra... PS2, Line 758: 0x26 & 0x8f;
@huayang If you think the changes are okay, please resolve this comment. Thanks.
MR01Value[FSP_0] default value is 0x26 AND MR01Value[FSP_0] default value is 0x56 at the begin of Mode register pre init at function vInitGlobalVariablesByCondition() so just define the value 0x26 & 0x8f or 0X6 all ok.