[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34805 )

Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API
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Patch Set 5:
> Patch Set 4:
>
> My test results for KBL:
> memsetting 1GiB of memory with different MTRR settings in NEM right after raminit:
>
> do_fsp_post_memory_init: took 9180 msec to clear 1GiB UC
> do_fsp_post_memory_init: took 9179 msec to clear 1GiB WPROT
> do_fsp_post_memory_init: took 39 msec to clear 1GiB WRCOMB
> do_fsp_post_memory_init: took 76 msec to clear 1GiB WRBACK
>
> The use of WRBACK in NEM causes postcar stage loading to fail. The use of WRCOMB seems fine, it still boots.

HI Patrick, are you really sure that WC took least time between all MTRR types. As per SDM, WC is not for read/write cacheable. btw, which address range you tried ?