29 May
2019
29 May
'19
12:01 a.m.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32842 )
Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/32842/5/src/southbridge/intel/fsp_rangeley/e... File src/southbridge/intel/fsp_rangeley/early_init.c:
https://review.coreboot.org/#/c/32842/5/src/southbridge/intel/fsp_rangeley/e... PS5, Line 43: write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_TMR_HALT); // disable watchdog timer line over 80 characters
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622
Gerrit-Change-Number: 32842
Gerrit-PatchSet: 5
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Gerrit-Reviewer: David Guckian
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Gerrit-Comment-Date: Tue, 28 May 2019 22:01:46 +0000
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