[coreboot-gerrit] Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51918 )

Change subject: mb/google/kukui: katsu: update the EDID and initial code
......................................................................

mb/google/kukui: katsu: update the EDID and initial code

The EDID and initial code are provided by STA (the vendor).

BUG=b:183969078
TEST=Boots on Chromebook Katsu and displayed developer firmware screen
successfully.

Signed-off-by: Sunway 
Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
index baf3dac..18e3cb7 100644
--- a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
+++ b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
@@ -9,7 +9,7 @@
    	.panel_bits_per_color = 8,
    	.panel_bits_per_pixel = 24,
    	.mode = {
-			.pixel_clock = 150451,
+			.pixel_clock = 165731,
    		.lvds_dual_channel = 0,
    		.refresh = 60,
    		.ha = 1200, .hbl = 210, .hso = 100, .hspw = 10,
@@ -20,7 +20,7 @@
    },
    .orientation = LB_FB_ORIENTATION_LEFT_UP,
    .init = {
-		INIT_DCS_CMD(0xB0, 0x41),
+		INIT_DCS_CMD(0xB0, 0x01),
    	INIT_DCS_CMD(0xC3, 0x4F),
    	INIT_DCS_CMD(0xC4, 0x40),
    	INIT_DCS_CMD(0xC5, 0x40),
@@ -63,13 +63,14 @@
    	INIT_DCS_CMD(0xD3, 0x04),
    	INIT_DCS_CMD(0xD4, 0x01),
    	INIT_DCS_CMD(0xD5, 0x00),
-		INIT_DCS_CMD(0xC6, 0x03),
+		INIT_DCS_CMD(0xD6, 0x03),
    	INIT_DCS_CMD(0xD7, 0x04),
    	INIT_DCS_CMD(0xD9, 0x01),
    	INIT_DCS_CMD(0xDB, 0x01),
    	INIT_DCS_CMD(0xE4, 0xF0),
    	INIT_DCS_CMD(0xE5, 0x0A),
    	INIT_DCS_CMD(0xB0, 0x00),
+		INIT_DCS_CMD(0xCC, 0x08),
    	INIT_DCS_CMD(0xC2, 0x08),
    	INIT_DCS_CMD(0xC4, 0x10),
    	INIT_DCS_CMD(0xB0, 0x02),