Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8645
-gerrit
commit 79bd0f0ae6dbf1d04f7fe213b6748cc14057145e Author: Tom Warren twarren@nvidia.com Date: Wed Jul 16 11:09:39 2014 -0700
ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed.
Also slipped in a minor name change in mainboard.c
BRANCH=none BUG=none TEST=none, no HW here for me to test on yet
Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren twarren@nvidia.com Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin adurbin@chromium.org (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones marc.jones@se-eng.com --- src/mainboard/google/rush_ryu/mainboard.c | 2 +- src/mainboard/google/rush_ryu/pmic.c | 61 ++++++--------------- src/mainboard/google/rush_ryu/pmic.h | 89 +++++++++++++++++++++++-------- 3 files changed, 83 insertions(+), 69 deletions(-)
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 9b8e354..dff5954 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -30,6 +30,6 @@ static void mainboard_enable(device_t dev) }
struct chip_operations mainboard_ops = { - .name = "rush", + .name = "rush_ryu", .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c index 5fc3b17..8d5ea7a 100644 --- a/src/mainboard/google/rush_ryu/pmic.c +++ b/src/mainboard/google/rush_ryu/pmic.c @@ -23,45 +23,31 @@ #include <device/i2c.h> #include <stdint.h> #include <stdlib.h> - -#include "boardid.h" #include "pmic.h" #include "reset.h"
+/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */ + enum { - AS3722_I2C_ADDR = 0x40 + TI65913_I2C_ADDR = 0x58 };
-struct as3722_init_reg { +struct ti65913_init_reg { u8 reg; u8 val; u8 delay; };
-static struct as3722_init_reg init_list[] = { - {AS3722_SDO0, 0x3C, 1}, - {AS3722_SDO1, 0x32, 0}, - {AS3722_LDO3, 0x59, 0}, - {AS3722_SDO2, 0x3C, 0}, - {AS3722_SDO3, 0x00, 0}, - {AS3722_SDO4, 0x00, 0}, - {AS3722_SDO5, 0x50, 0}, - {AS3722_SDO6, 0x28, 1}, - {AS3722_LDO0, 0x8A, 0}, - {AS3722_LDO1, 0x00, 0}, - {AS3722_LDO2, 0x10, 0}, - {AS3722_LDO4, 0x00, 0}, - {AS3722_LDO5, 0x00, 0}, - {AS3722_LDO6, 0x00, 0}, - {AS3722_LDO7, 0x00, 0}, - {AS3722_LDO9, 0x00, 0}, - {AS3722_LDO10, 0x00, 0}, - {AS3722_LDO11, 0x00, 1}, +static struct ti65913_init_reg init_list[] = { +//TODO(twarren@nvidia.com): Add slams back to defaults +// {TI65913_SMPS12_CTRL, 0x01, 0}, +// {TI65913_SMPS12_VOLTAGE, 0x38, 0}, +//etc. };
static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) { - if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { + if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ @@ -75,38 +61,23 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) static void pmic_slam_defaults(unsigned bus) { int i; + for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct as3722_init_reg *reg = &init_list[i]; + struct ti65913_init_reg *reg = &init_list[i]; pmic_write_reg(bus, reg->reg, reg->val, reg->delay); } }
void pmic_init(unsigned bus) { - /* - * Don't need to set up VDD_CORE - already done - by OTP - * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. - * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. - */ + /* Don't need to set up VDD_CORE - already done - by EC ?? */
/* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus);
- /* SDO0: Set VDD_CPU to 1.2V. */ - pmic_write_reg(bus, 0x00, 0x50, 1); - - /* SDO6: Set VDD_GPU to 1.0V. */ - pmic_write_reg(bus, 0x06, 0x28, 1); - - /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */ - pmic_write_reg(bus, 0x12, 0x10, 1); - - /* - * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set - * the value (register 0x20 bit 4) - */ - pmic_write_reg(bus, 0x0c, 0x07, 0); - pmic_write_reg(bus, 0x20, 0x10, 1); + /* A44: Set VDD_CPU to 1.0V. */ + pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); + pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0);
printk(BIOS_DEBUG, "PMIC init done\n"); } diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h index b56c513..1f102a7 100644 --- a/src/mainboard/google/rush_ryu/pmic.h +++ b/src/mainboard/google/rush_ryu/pmic.h @@ -17,32 +17,75 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__ -#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__ +#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ +#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
+/* A44/Ryu has a TI 65913 PMIC */ enum { - AS3722_SDO0 = 0, - AS3722_SDO1, - AS3722_SDO2, - AS3722_SDO3, - AS3722_SDO4, - AS3722_SDO5, - AS3722_SDO6, - - AS3722_LDO0 = 0x10, - AS3722_LDO1, - AS3722_LDO2, - AS3722_LDO3, - AS3722_LDO4, - AS3722_LDO5, - AS3722_LDO6, - AS3722_LDO7, - - AS3722_LDO9 = 0x19, - AS3722_LDO10, - AS3722_LDO11, + TI65913_SMPS12_CTRL = 0x20, + TI65913_SMPS12_TSTEP, + TI65913_SMPS12_FORCE, + TI65913_SMPS12_VOLTAGE, + + TI65913_SMPS3_CTRL, + TI65913_SMPS3_VOLTAGE = 0x27, + + TI65913_SMPS45_CTRL = 0x28, + TI65913_SMPS45_TSTEP, + TI65913_SMPS45_FORCE, + TI65913_SMPS45_VOLTAGE, + + TI65913_SMPS6_CTRL = 0x2C, + TI65913_SMPS6_TSTEP, + TI65913_SMPS6_FORCE, + TI65913_SMPS6_VOLTAGE, + + TI65913_SMPS7_CTRL = 0x30, + TI65913_SMPS7_VOLTAGE = 0x33, + + TI65913_SMPS8_CTRL = 0x34, + TI65913_SMPS8_TSTEP, + TI65913_SMPS8_FORCE, + TI65913_SMPS8_VOLTAGE, + + TI65913_SMPS9_CTRL = 0x38, + TI65913_SMPS9_VOLTAGE = 0x3B, + + TI65913_SMPS10_CTRL = 0x3C, + TI65913_SMPS10_STATUS = 0x3F, + + TI65913_LDO1_CTRL = 0x50, + TI65913_LDO1_VOLTAGE, + TI65913_LDO2_CTRL, + TI65913_LDO2_VOLTAGE, + TI65913_LDO3_CTRL, + TI65913_LDO3_VOLTAGE, + TI65913_LDO4_CTRL, + TI65913_LDO4_VOLTAGE, + TI65913_LDO5_CTRL, + TI65913_LDO5_VOLTAGE, + TI65913_LDO6_CTRL, + TI65913_LDO6_VOLTAGE, + TI65913_LDO7_CTRL, + TI65913_LDO7_VOLTAGE, + TI65913_LDO8_CTRL, + TI65913_LDO8_VOLTAGE, + TI65913_LDO9_CTRL, + TI65913_LDO9_VOLTAGE, + + TI65913_LDOLN_CTRL = 0x62, + TI65913_LDOLN_VOLTAGE = 0x63, + TI65913_LDOUSB_CTRL = 0x64, + TI65913_LDOUSB_VOLTAGE = 0x65, + + TI65913_LDO_CTRL = 0x6A, + TI65913_LDO_PD_CTRL1 = 0x6B, + TI65913_LDO_PD_CTRL2 = 0x6C, + + TI65913_LDO_SHORT_STATUS1 = 0x6D, + TI65913_LDO_SHORT_STATUS2 = 0x6E, };
void pmic_init(unsigned bus);
-#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */ +#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */