[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/sb: Gate FCH AH2ALB clocks

[Matt Papageorge (Code Review)]

Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42829 )

Change subject: soc/amd/picasso/sb: Gate FCH AH2ALB clocks
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42829/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42829/1//COMMIT_MSG@9 
PS1, Line 9: AH2ALB
> What is this block? And should we always unconditionally gate the clocks?

A-Link to AHB bridge, part of the AMBA fabric.

Looks like this was spelled different in the FSP vs the PPR. I will fix to clarify as we should follow the PPR.

My understanding is these are always gated in Raven/Picasso.