Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5719
-gerrit
commit c7079b8c9534ccb53a15d1103b54bcff2becd9ff Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon May 12 15:00:03 2014 +0300
intel: Drop obsolete comments on MTRR usage
Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation.
Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/include/device/device.h | 4 ---- src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 ----------- src/northbridge/intel/nehalem/northbridge.c | 11 ----------- src/northbridge/intel/sandybridge/northbridge.c | 11 ----------- 4 files changed, 37 deletions(-)
diff --git a/src/include/device/device.h b/src/include/device/device.h index fd26c04..a4ef456 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -213,10 +213,6 @@ void fixed_mem_resource(device_t dev, unsigned long index,
/* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. - * - * Current MTRR setup creates exclusive uncacheable holes for uma_resource() - * only and these are allowed to overlap any ram_resource(). This approach - * is used for all UMA except Intel Sandy/IvyBridge. */ #define ram_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index d5b1575..2922ca0 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -102,17 +102,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size;
- /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index d94bc09..639d245 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -134,17 +134,6 @@ static void mc_read_resources(device_t dev) ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768));
- /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5440140..1fd252b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -100,17 +100,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size;
- /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {