[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/picasso/acpi: don't announce unimplemented duty cycle control

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73420 )

Change subject: soc/amd/picasso/acpi: don't announce unimplemented duty cycle control
......................................................................

soc/amd/picasso/acpi: don't announce unimplemented duty cycle control

Picasso neither has the corresponding P_CNT register implemented nor
writes a _PTC ACPI object that would specify the P_CNT register. The
Picasso UEFI reference code also sets the duty_width FADT entry to 0.
This also aligns the Picasso code with the Cezanne code in this regard.

Signed-off-by: Felix Held 
Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860
---
M src/soc/amd/picasso/acpi.c
1 file changed, 17 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/73420/1

diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 89ca502..7244a11 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -86,8 +86,8 @@
       overridden by the _CST packages in the processor devices. */
    fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
    fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
-	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
+	fadt->duty_offset = 0;	/* Not supported */
+	fadt->duty_width = 0;	/* Not supported */
    fadt->day_alrm = RTC_DATE_ALARM;
    fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */
    fadt->flags |=	ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */