Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35509 )
Change subject: mb/google/drallion: Disable GBE in firmware for drallion variants ......................................................................
mb/google/drallion: Disable GBE in firmware for drallion variants
BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.corp-partner.google.com Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King mathewk@chromium.org Reviewed-by: Bora Guvendik bora.guvendik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index f2367ff..8cb1aa3 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -417,6 +417,6 @@ device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end