Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... PS5, Line 177: enable_ramstage_caching(top_of_ram, top_of_ram_size);
*sigh* […]
Maybe add a function like postcar_frame_add_romcache() but for both setting up the postcar frame MTRR as setting up the MTRR to speed up operation on the area below cbmem?
@Arthur: CL is here https://review.coreboot.org/c/coreboot/+/34805
Also I would expect the real perfomance come from enabling WB for TSEG here.
here is the snapshot of MTRR at romstage end (before loading postcar)
0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB 0x0000007ffffc0800: PHYMASK0: Length = 0x0000000000040000, Valid 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP 0x0000000fff000800: PHYMASK1: Length = 0x0000007001000000, Valid
and entire cbmem region here whatever we have marked from top_of_ram-16MB to 16MB is out of MTRR snapshot and majority of activities lies in this region.
And due to below reason, we can't make top_of_ram region as WB. So intention here is to make required region as WP to make use of caching for "smaller" windows for now till we loading postcar and postcar MTRR stack frame again sets things up as per expectation.
Anyways: Making any RAM region WB cacheable here conflicts with 'invd' in exit_car.S.
with this CL, MTRR snapshot at romstage before loading postcar
0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB 0x0000007ffffc0800: PHYMASK0: Length = 0x0000000000040000, Valid 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid 0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP 0x0000007fff000800: PHYMASK2: Length = 0x0000000001000000, Valid
and after loading postcar
0x00000000ff000005: PHYBASE0: Address = 0x00000000ff000000, WP 0x0000007fff000800: PHYMASK0: Length = 0x0000000001000000, Valid 0x0000000099000006: PHYBASE1: Address = 0x0000000099000000, WB 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid