[coreboot-gerrit] Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 )

Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
......................................................................

drivers/amd/agesa/romstage: Only mark cbmem as UC if needed

Now cbmem is flushed to dram before calling postcar stage.

UNTESTED.

Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3
Signed-off-by: Arthur Heymans 
---
M src/drivers/amd/agesa/mtrr_fixme.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1

diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
index bbb9eb0..9e63425 100644
--- a/src/drivers/amd/agesa/mtrr_fixme.c
+++ b/src/drivers/amd/agesa/mtrr_fixme.c
@@ -51,6 +51,10 @@
    if (s3resume)
    	return;

+	/* We worry about cbmem hitting dram later */
+	if (clflush_supported())
+		return;
+
    /* For normal path, INIT_POST has returned with all
     * memory set WB cacheable. But we need CBMEM as UC
     * to make CAR teardown with invalidation without