[coreboot-gerrit] [S] Change in coreboot[master]: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68223 )

Change subject: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work
......................................................................

[UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work

FSP-M seems to do something to make PCIe ports work. However, we need to
have PCIe ports working in bootblock for the NC FPGA. Add a bit of magic
register poking that (hopefully) allows the PCIe ports to work earlier.

UNTESTED.

Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons 
---
M src/mainboard/siemens/mc_apl1/bootblock.c
1 file changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/1

diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c
index a858f1b..aaf8eb9 100644
--- a/src/mainboard/siemens/mc_apl1/bootblock.c
+++ b/src/mainboard/siemens/mc_apl1/bootblock.c
@@ -2,7 +2,32 @@

#include <baseboard/variants.h>
 #include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <intelblocks/gpio.h>
+#include <types.h>
+
+static void try_to_make_pcie_work(void)
+{
+	const pci_devfn_t pcie_rps[] = {
+		PCI_DEV(0, 0x13, 0), PCI_DEV(0, 0x13, 1), PCI_DEV(0, 0x13, 2),
+		PCI_DEV(0, 0x13, 3), PCI_DEV(0, 0x14, 0), PCI_DEV(0, 0x14, 1),
+	};
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(pcie_rps); i++) {
+		const pci_devfn_t dev = pcie_rps[i];
+
+		if (pci_read_config16(dev, PCI_VENDOR_ID) == 0xffff)
+			continue;
+
+		/*
+		 * Needs to be done "immediately after PERST# de-assertion"
+		 * as per IAFW spec volume 2 (doc 559810)
+		 */
+		pci_and_config32(dev, 0x338, ~(1 << 26));	/* BLKDQDA */
+		pci_and_config32(dev,  0xf4, ~(1 <<  2));	/* BLKPLLEN */
+	}
+}

void bootblock_mainboard_early_init(void)
 {
@@ -11,4 +36,7 @@

pads = variant_early_gpio_table(&num);
    gpio_configure_pads(pads, num);
+
+	if (CONFIG(BOARD_SIEMENS_MC_APL2))
+		try_to_make_pcie_work();
 }