EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
I don't know why schematic shift the clksrc. Ideal is same clkreq with same clksrc.. […]
I think we can use a structure for this but need to rewrite the fsp_param. What do you think? This is pretty like IBV bios define in config file. And we don't care about the detail just refer the schematic to fill it.
struct { pcie_port, ex:7 clksrc, ex:4 clkreq, ex:3 } pcie_t;
PcieRpEnable[pcie_port] = 1 PcieRpLtrEnable[pcie_port] = 1 PcieClkSrcClkReq[clkreq] = clksrc PcieClkSrcUsage[clksrc] = pcie_port