[coreboot-gerrit] [XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro.

Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email )

Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
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Patch Set 4:

(1 comment)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/86111/comment/d772110b_94164fdc?usp... :
PS4, Line 202: ps->prev_sleep_state == ACPI_S5 
We are only issuing a warm reset post UFS disablement in the S5 flow. What would happen if the reset type is not S5 (and some other reset type introduces this issue) and UFS is disabled but does not hit warm reset?

I guess the only corner case you have seen so far where UFS is disabled but S0ix is not working (and it works after warm reset) is mostly due to the fact that you are disabling UFS on all boots but only issuing a system reset in the S5 flow (so PMC is not aware of certain change in UFS state).

I would like to understand what sleep types, other than S5, are encountering this issue. There are only four sleep types: S0, S3, S4, and S5. S3 and S4 are not supported, and S0 represents warm resets. This leaves us with S5 only. Does it make sense to check CSE reset types (looking at the CSE FW status register along with the S5 type) to cover this corner case as well?