Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55254 )
Change subject: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon ......................................................................
Patch Set 1:
(3 comments)
File src/soc/intel/alderlake/romstage/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/d5a1f66b_abc33a02 PS1, Line 147: if(cse_get_rw_rdev(&desc_dev) < 0) space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/ecaf8a43_a0338103 PS1, Line 155: if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x44 ) { space prohibited before that close parenthesis ')'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120881): https://review.coreboot.org/c/coreboot/+/55254/comment/ae3224fc_d86a7c11 PS1, Line 204: * if CSE RW blob's version is different from CSE RW version. code indent should use tabs where possible