[coreboot-gerrit] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges

[Werner Zeh (Code Review)]

Attention is currently required from: Mario Scheithauer.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )

Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges
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Patch Set 2: Code-Review+1

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/63931/comment/d58a216b_c137e9a8 
PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
There is just one bridge on this board.