Attention is currently required from: Iru Cai, Iru Cai (vimacs). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54745 )
Change subject: Documentation: update Haswell document on SPD ......................................................................
Patch Set 2:
(1 comment)
File Documentation/northbridge/intel/haswell/mrc.bin.md:
https://review.coreboot.org/c/coreboot/+/54745/comment/7e06f392_801b3852 PS2, Line 102: The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied : by 2. For example, if the addresses read through `i2c-tools` when booted from : vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and : `0xa4`. This is because the I2C addresses are 7 bits long. I believe the added paragraph is likely to confuse readers: do the SPD addresses in mainboard code need to be left-shifted or not?
Instead of adding a new paragraph, I'd change this paragraph. The `spdi->addresses` values programmed in mainboard code are left-shifted in wrapper code to match the format MRC expects, so the SPD addresses in `spdi->addresses` do *not* need to be left-shifted.