David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 52:
(619 comments)
Patch Set 3:
(169 comments)
Just clearing out some stale lint comments - I think I got all the ones up thru (including) to PS4
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 182: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 192: socket, stack, ioapic_id, ri->IoApicBase + 0x1000, gsi_base);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 193: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 668: PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 685: current += acpi_create_dmar_ds_pci(current, bus, CBDMA_DEV_NUM, cbdma_func_id);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 695: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 696: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 712: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 723: (*((volatile u32 *)(u32)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { // BIT 15
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 751: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 754: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 756: __func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1054: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1056: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 392: /* update bridge range from child bridge range */
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 392: /* update bridge range from child bridge range */
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
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Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 392: /* update bridge range from child bridge range */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 392: /* update bridge range from child bridge range */
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
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https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
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Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 55: UINT8 SocketFirstBus;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 56: UINT8 SocketLastBus;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 57: UINT8 segmentSocket;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 58: UINT8 PcieSegment;
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 60: UINT8 stackPresentBitmap;
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 55: UINT8 SocketFirstBus;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 57: UINT8 segmentSocket;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 58: UINT8 PcieSegment;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
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Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
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Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
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Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
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