[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

[Surendranath R Gurivireddy (Code Review)]

Surendranath R Gurivireddy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36519 )

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
......................................................................

soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

Signed-off-by: Surendranath Gurivireddy 
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36519/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0713ef4..27b109d 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -273,6 +273,9 @@
    	params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
    }

+       /* Disable USB2 PHY Power gating */
+       params->PchUsb2PhySusPgEnable = 0;
+
    for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
    	params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
    	params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;