[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Tidy up comments and cosmetics

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43167 )

Change subject: nb/intel/pineview: Tidy up comments and cosmetics
......................................................................

nb/intel/pineview: Tidy up comments and cosmetics

Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/pineview/acpi/hostbridge.asl
M src/northbridge/intel/pineview/acpi/peg.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
3 files changed, 8 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43167/1

diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl
index 434ed07..be5579d 100644
--- a/src/northbridge/intel/pineview/acpi/hostbridge.asl
+++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl
@@ -35,7 +35,7 @@
    	,	11,	/*
    	DMBR,	20,	/* DMIBAR */

-		// ...
+		/* ... */

Offset (0x90),	/* PAM0 */
    	,	 4,
@@ -73,18 +73,15 @@
    	,	 2,

Offset (0xa0),	/* Top of Memory */
-		TOM,	8,
+		TOM,	 8,

Offset (0xb0),	/* Top of Low Used Memory */
    	,	 4,
    	TLUD,	12,
-
    }

}

-
-/* Current Resource Settings */
 Name (MCRS, ResourceTemplate()
 {
    /* Bus Numbers */
@@ -199,6 +196,7 @@
    		0x00005000,,, TPMR)
 })

+/* Current Resource Settings */
 Method (_CRS, 0, Serialized)
 {
    /* Find PCI resource area in MCRS */
@@ -206,7 +204,8 @@
    CreateDwordField(MCRS, ^PM01._MAX, PMAX)
    CreateDwordField(MCRS, ^PM01._LEN, PLEN)

-	/* Fix up PCI memory region:
+	/*
+	 * Fix up PCI memory region:
     * Enter actual TOLUD. The TOLUD register contains bits 27-31 of
     * the top of memory address.
     */
diff --git a/src/northbridge/intel/pineview/acpi/peg.asl b/src/northbridge/intel/pineview/acpi/peg.asl
index f85a22c..6a67238 100644
--- a/src/northbridge/intel/pineview/acpi/peg.asl
+++ b/src/northbridge/intel/pineview/acpi/peg.asl
@@ -12,16 +12,15 @@
    			Package() { 0x0000ffff, 0, 0, 16 },
    			Package() { 0x0000ffff, 1, 0, 17 },
    			Package() { 0x0000ffff, 2, 0, 18 },
-				Package() { 0x0000ffff, 3, 0, 19 }
+				Package() { 0x0000ffff, 3, 0, 19 },
    		})
    	} Else {
    		Return (Package() {
    			Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 },
    			Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 },
    			Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 }
+				Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 },
    		})
    	}
-
    }
 }
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index 074e900..3579a26 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -10,9 +10,7 @@
    Name (_HID, EISAID("PNP0C02"))
    Name (_UID, 1)

-	/* This does not seem to work correctly yet - set values statically for
-	 * now.
-	 */
+	/* This does not seem to work correctly yet - set values statically for now. */

Name (PDRS, ResourceTemplate() {
    	Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)