[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/i945: Put stage cache in TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 )

Change subject: nb/intel/i945: Put stage cache in TSEG
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Patch Set 37:

(1 comment)

https://review.coreboot.org/#/c/25603/37//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/25603/37//COMMIT_MSG@16 
PS37, Line 16:
> So was resume broken, or is it some preparation work?

No this is simply a different and supposedly better place in ram to put the cached postcar stage and ramstage. Before those were put in cbmem, now in TSEG.