Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54303 )
Change subject: mb/google/guybrush: Enable PCIe L1 Substates ......................................................................
mb/google/guybrush: Enable PCIe L1 Substates
Currently cannot complete POST with this change. Investigating now
BUG=b:188123142 TEST=Currently non-functional due to hang in POST
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/port_descriptors.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/54303/1
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 5a7cd8a..21b1f3c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -36,6 +36,7 @@ select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE
config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 540d3d1..6de1879 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,6 +14,8 @@ .device_number = 2, .function_number = 1, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, .gpio_group_id = GPIO_29, @@ -27,6 +29,8 @@ .device_number = 2, .function_number = 2, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, .gpio_group_id = GPIO_70, @@ -40,6 +44,8 @@ .device_number = 2, .function_number = 3, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, .gpio_group_id = GPIO_18, @@ -53,6 +59,8 @@ .device_number = 2, .function_number = 4, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, .gpio_group_id = GPIO_40,