Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/54e95dfa_5a41a5bc PS5, Line 1014: /*
This is not applicable if CSE Lite is integrated instead CSE Consumer SKU since Chrome platform uses HMRFPO mechanism to update the CSE Region (specifically CSE RW). So, please add below code the function. Please not Chrome platform doesn't use FPT tool to update the CSE region.
if (CONFIG(CONFIG_SOC_INTEL_CSE_LITE_SKU)) return;
Sure, if this is the requirement for Chrome OS then I have below opens: 1. Please update the ME BWG to document the expectation for applicable CSE LITE SKU. 2. Please raise a bug for FSP, as today in ADL FSP does below highlighted programming as well unconditionally (please investigate inside FSP Notify API code) without any flag about LITE or consumer, wondering how so far on TGL, JSL and ADL CSE FW update works with below implementation inside FSP. Do you want me to raise those 2 bugs ?
"BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) prior to transferring control to the OS."