Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16192
-gerrit
commit 4462c086d8aac812b20cd759f0fcd63bddcaf53d Author: Aaron Durbin adurbin@chromium.org Date: Thu Aug 11 14:40:09 2016 -0500
Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/x86/Kconfig | 7 ------- src/drivers/elog/elog.c | 2 +- src/drivers/spi/Kconfig | 7 +++++++ src/lib/cbfs_spi.c | 2 +- src/mainboard/google/chell/Kconfig | 4 ---- src/mainboard/google/cosmos/Kconfig | 2 +- src/mainboard/google/foster/Kconfig | 2 +- src/mainboard/google/glados/Kconfig | 4 ---- src/mainboard/google/gru/Kconfig | 2 +- src/mainboard/google/gru/bootblock.c | 2 +- src/mainboard/google/lars/Kconfig | 4 ---- src/mainboard/google/nyan/Kconfig | 2 +- src/mainboard/google/nyan_big/Kconfig | 2 +- src/mainboard/google/nyan_blaze/Kconfig | 2 +- src/mainboard/google/oak/Kconfig | 2 +- src/mainboard/google/purin/Kconfig | 4 ---- src/mainboard/google/reef/Kconfig | 4 ---- src/mainboard/google/smaug/Kconfig | 2 +- src/mainboard/google/urara/Kconfig | 2 +- src/mainboard/google/veyron/Kconfig | 2 +- src/mainboard/google/veyron/bootblock.c | 2 +- src/mainboard/google/veyron_brain/Kconfig | 2 +- src/mainboard/google/veyron_brain/bootblock.c | 2 +- src/mainboard/google/veyron_danger/Kconfig | 2 +- src/mainboard/google/veyron_danger/bootblock.c | 2 +- src/mainboard/google/veyron_emile/Kconfig | 2 +- src/mainboard/google/veyron_emile/bootblock.c | 2 +- src/mainboard/google/veyron_mickey/Kconfig | 2 +- src/mainboard/google/veyron_mickey/bootblock.c | 2 +- src/mainboard/google/veyron_rialto/Kconfig | 2 +- src/mainboard/google/veyron_rialto/bootblock.c | 2 +- src/mainboard/google/veyron_romy/Kconfig | 2 +- src/mainboard/google/veyron_romy/bootblock.c | 2 +- src/mainboard/intel/amenia/Kconfig | 4 ---- src/mainboard/intel/kunimitsu/Kconfig | 4 ---- src/soc/mediatek/mt8173/spi.c | 2 +- src/vboot/vbnv_flash.c | 3 ++- 37 files changed, 36 insertions(+), 63 deletions(-)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 54a1fef..c4507bc 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -147,13 +147,6 @@ config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING the SPI contents to RAM before performing the load can speed up the boot process.
-config BOOT_MEDIA_SPI_BUS - int - default 0 - depends on SPI_FLASH - help - Most x86 systems which boot from SPI flash boot using bus 0. - config SOC_SETS_MSRS bool default n diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 55b8974..0b7dee3 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -751,7 +751,7 @@ int elog_init(void) elog_debug("elog_init()\n");
/* Probe SPI chip. SPI controller must already be initialized. */ - elog_spi = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); + elog_spi = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); if (!elog_spi) { printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); return -1; diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 35435a6..ee48d67 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -23,6 +23,13 @@ config SPI_FLASH
if SPI_FLASH
+# Keep at 0 because lots of boards assume this default. +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 0 + help + Which SPI bus the boot device is connected to. + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n if COMMON_CBFS_SPI_WRAPPER diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c index 2677ac4..bbe9125 100644 --- a/src/lib/cbfs_spi.c +++ b/src/lib/cbfs_spi.c @@ -59,7 +59,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache);
void boot_device_init(void) { - int bus = CONFIG_BOOT_MEDIA_SPI_BUS; + int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; int cs = 0;
if (spi_flash_info != NULL) diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index 6fcdad4..38db373 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT int default 18
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/chell" diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index 19d5955..62cd821 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index 3de9a4c..8a9e53d 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -60,7 +60,7 @@ config FOSTER_BCT_CFG_EMMC
endchoice
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 7 depends on FOSTER_BCT_CFG_SPI diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 83049b7..e70094f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -32,10 +32,6 @@ config IRQ_SLOT_COUNT int default 18
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/glados" diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index d5733c8..3150839 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -67,7 +67,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 5
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 1
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 8f88043..e80f4a3 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -63,7 +63,7 @@ void bootblock_mainboard_init(void) /* Set pinmux and configure spi flashrom. */ write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
/* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5); diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 1bcb576..2a4973e 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -36,10 +36,6 @@ config IRQ_SLOT_COUNT int default 18
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "google/lars" diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index fedf18f..e68ad4e 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -62,7 +62,7 @@ config NYAN_BCT_CFG_EMMC
endchoice
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 5c4009a..3f94637 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -63,7 +63,7 @@ config NYAN_BIG_BCT_CFG_EMMC
endchoice
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BIG_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index a11b3eb..e47ebfa 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -64,7 +64,7 @@ config NYAN_BLAZE_BCT_CFG_EMMC
endchoice
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 6 depends on NYAN_BLAZE_BCT_CFG_SPI diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 975cdab..1228cff 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -60,7 +60,7 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 9
diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index d415211..eabab2b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config DRAM_SIZE_MB int default 256 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5fafa8b..b7813b7 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -12,10 +12,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select SYSTEM_TYPE_LAPTOP
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config CHROMEOS select LID_SWITCH
diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 000304f..15ff2b3 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -67,7 +67,7 @@ config SMAUG_BCT_CFG_EMMC
endchoice
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int "SPI bus with boot media ROM" range 1 7 depends on SMAUG_BCT_CFG_SPI diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 6054a02..e7b9e0e 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -52,7 +52,7 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xB8101500
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 1
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index c21cd3f..b6a687c 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index c355410..1f4eec2 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -64,7 +64,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
/* spi0 for chrome ec */ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0); diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index 41a7456..1348f23 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index cb1dc71..ab667d8 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -48,7 +48,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_danger/bootblock.c +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_emile/Kconfig b/src/mainboard/google/veyron_emile/Kconfig index 059dd1f..d5884f9 100644 --- a/src/mainboard/google/veyron_emile/Kconfig +++ b/src/mainboard/google/veyron_emile/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_emile/bootblock.c b/src/mainboard/google/veyron_emile/bootblock.c index 2fe913e..7261275 100644 --- a/src/mainboard/google/veyron_emile/bootblock.c +++ b/src/mainboard/google/veyron_emile/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 6f489ff..d1a481f 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 9321812..b6d3f65 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index aab05a6..dae046b 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index c151727..e91034e 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -47,7 +47,7 @@ config MAINBOARD_VENDOR string default "Google"
-config BOOT_MEDIA_SPI_BUS +config BOOT_DEVICE_SPI_FLASH_BUS int default 2
diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c index f855a26..b95a265 100644 --- a/src/mainboard/google/veyron_romy/bootblock.c +++ b/src/mainboard/google/veyron_romy/bootblock.c @@ -66,7 +66,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
setup_chromeos_gpios(); } diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index d4e2c56..9549672 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,10 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config CHROMEOS select LID_SWITCH
diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 56590da..67143ca 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -35,10 +35,6 @@ config IRQ_SLOT_COUNT int default 18
-config BOOT_MEDIA_SPI_BUS - int - default 0 - config MAINBOARD_DIR string default "intel/kunimitsu" diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index dc674f3..c35b1fc 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -170,7 +170,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) assert(read32(&eslave->regs->spi_cfg0_reg) != 0); spi_sw_reset(eslave->regs); return &eslave->slave; - case CONFIG_BOOT_MEDIA_SPI_BUS: + case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: slave.bus = bus; slave.cs = cs; slave.force_programmer_specific = 1; diff --git a/src/vboot/vbnv_flash.c b/src/vboot/vbnv_flash.c index 8b60be2..717ff23 100644 --- a/src/vboot/vbnv_flash.c +++ b/src/vboot/vbnv_flash.c @@ -136,7 +136,8 @@ static int vbnv_flash_probe(void) struct vbnv_flash_ctx *ctx = car_get_var_ptr(&vbnv_flash);
if (!ctx->flash) { - ctx->flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0); + ctx->flash = + spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); if (!ctx->flash) { printk(BIOS_ERR, "failed to probe spi flash\n"); return 1;