John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31131 )
Change subject: soc/intel/apollolake: Sync fsp upd structure update ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h File src/soc/intel/apollolake/chip.h:
https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@173 PS2, Line 173: * value. Default is 0 to not changing default IF value.
What are the valid values? And what do the values mean?
The change is sync to fsp 2.0.9 upd update. Can we specify value to mainboard code? Final value will be shared along with validation results. Note: fsp currently applies IF value 0x12.
https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@178 PS2, Line 178: .
by 40mV?
Can we specify value to mainboard code? Note: If set TRUE, the usb3 LDO is increased by 40mV.
https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@184 PS2, Line 184: * the PMIC Vdd2 voltage.
What are the valid values?
Can we specify value to mainboard code? Note: PMIC vdd2 is by default with 1.2v. PmicVdd2Voltage can be configured to adjust vdd2 through BUCK5_VID[3:2]: 00=1.0v, 01=1.15v, 10=1.24v, 11=1.20v(default). It is intended to up to 1.24v as