[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update chip files

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )

Change subject: soc/intel/tigerlake: Update chip files
......................................................................

Patch Set 33:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... 
PS33, Line 120: default 7 if SOC_INTEL_TIGERLAKE
              : 	default 16 if SOC_INTEL_JASPERLAKE
> What is this based on? I think FSP allows maximum 16 entries for ClkReq and ClkSrc. […]

Yes Furquan, For JSL this needs to be updated. Updated Bug below to track this  as well.

https://partnerissuetracker.corp.google.com/issues/146884608#comment2