[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/cannonlake: Add PsysPmax setting

[Gaggery Tsai (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31505

to look at the new patch set (#3).

Change subject: src/soc/intel/cannonlake: Add PsysPmax setting
......................................................................

src/soc/intel/cannonlake: Add PsysPmax setting

This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.

BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
     in FSP to print the PsysPmax value before sending to Pcode, ensure
     the setting is correctly programmed.

Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31505/3