[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add support to initialize DDR4 Memory

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )

Change subject: soc/intel/tigerlake: Add support to initialize DDR4 Memory
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Patch Set 23:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39847/23/src/soc/intel/tigerlake/me... 
File src/soc/intel/tigerlake/meminit_tgl.c:

https://review.coreboot.org/c/coreboot/+/39847/23/src/soc/intel/tigerlake/me... 
PS23, Line 410: 			if (half_populated && (i == 1)) {
> half_populated is means i%2? 1,3,5,7.. […]

DDR4 interface supports 2 channels. When configuration is half populated, then channel 1 is left empty. DQ/DQS UPDs 4,5,6,7 map to channel 1, hence they are left empty.