[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Take ITSS polarity snaphot after GPIO configura...

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31246

Change subject: soc/intel/cannonlake: Take ITSS polarity snaphot after GPIO configuration
......................................................................

soc/intel/cannonlake: Take ITSS polarity snaphot after GPIO configuration

This implementation moves saving  ITSS IPCx regsister snaphsot after
the GPIO pad configuration has configured the polarity bits for active
low interrupts.

BUG=b:123315212
TEST=Verify the ITSS polarities set in ITSS IPCx registers are correctly
     restored for active low interrupts ater FSP-S call.

Change-Id: Id7b6f732759538ca41c872308727b1d87c2c5d85
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31246/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 4604d80..541155d 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -142,10 +142,6 @@

void soc_init_pre_device(void *chip_info)
 {
-	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
-	 * default policy that doesn't honor boards' requirements. */
-	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
    /* Perform silicon specific init. */
    fsp_silicon_init(romstage_handoff_is_resume());

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 866d9c8..595069b 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -19,8 +19,10 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>
@@ -87,6 +89,9 @@
    }

mainboard_silicon_init_params(params);
+	/* Snapshot the current GPIO IRQ polarities just after GPIO pad configuration.
+	 * FSP is setting a default policy that doesn't honor boards' requirements. */
+	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);

/* Unlock upper 8 bytes of RTC RAM */
    params->PchLockDownRtcMemoryLock = 0;