[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure RP setting

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40262

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Configure RP setting
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soc/intel/tigerlake: Configure RP setting

Adding LTR and AER configuration to the root ports config

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim 
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 11 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40262/5