[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/pch: Drop `acpi_sci_irq` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46888 )

Change subject: soc/intel/broadwell/pch: Drop `acpi_sci_irq` function
......................................................................

soc/intel/broadwell/pch: Drop `acpi_sci_irq` function

The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.

Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/pch/acpi.c
M src/soc/intel/broadwell/pch/fadt.c
M src/soc/intel/broadwell/pch/pm.h
M src/soc/intel/broadwell/pch/pmutil.c
4 files changed, 2 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46888/1

diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c
index 14aa9ce..4b307a1 100644
--- a/src/soc/intel/broadwell/pch/acpi.c
+++ b/src/soc/intel/broadwell/pch/acpi.c
@@ -1,18 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
-#include <acpi/acpigen.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
-#include <types.h>
-#include <soc/intel/broadwell/pch/pch.h>
-#include <soc/intel/broadwell/pch/pm.h>

unsigned long acpi_fill_madt(unsigned long current)
 {
-	int sci = acpi_sci_irq();
-	uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
-
    /* Local APICs */
    current = acpi_create_madt_lapics(current);

@@ -22,14 +15,9 @@
    /* INT_SRC_OVR */
    current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 0, 2, 0);

-	if (sci >= 20)
-		flags |= MP_IRQ_POLARITY_LOW;
-	else
-		flags |= MP_IRQ_POLARITY_HIGH;
-
    /* SCI */
    current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, sci, sci, flags);
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);

return current;
 }
diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c
index e30941e..5679541 100644
--- a/src/soc/intel/broadwell/pch/fadt.c
+++ b/src/soc/intel/broadwell/pch/fadt.c
@@ -10,7 +10,7 @@
 {
    const uint16_t pmbase = ACPI_BASE_ADDRESS;

-	fadt->sci_int = acpi_sci_irq();
+	fadt->sci_int = 9;

if (permanent_smi_handler()) {
    	fadt->smi_cmd = APM_CNT;
diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h
index 352394c..40467ed 100644
--- a/src/soc/intel/broadwell/pch/pm.h
+++ b/src/soc/intel/broadwell/pch/pm.h
@@ -139,9 +139,6 @@
 void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);

-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);

diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index 401431a..cc61715 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -413,34 +413,6 @@
    outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD));
 }

-int acpi_sci_irq(void)
-{
-	int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL;
-	int sci_irq = 9;
-
-	/* Determine how SCI is routed. */
-	switch (scis) {
-	case SCIS_IRQ9:
-	case SCIS_IRQ10:
-	case SCIS_IRQ11:
-		sci_irq = scis - SCIS_IRQ9 + 9;
-		break;
-	case SCIS_IRQ20:
-	case SCIS_IRQ21:
-	case SCIS_IRQ22:
-	case SCIS_IRQ23:
-		sci_irq = scis - SCIS_IRQ20 + 20;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
-		sci_irq = 9;
-		break;
-	}
-
-	printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
-	return sci_irq;
-}
-
 int platform_is_resuming(void)
 {
    if (!(inw(get_pmbase() + PM1_STS) & WAK_STS))